Main Page

Design process

Below is the basic design process for electronic systems. Our habit at ecosat of never following it has been a common cause of headaches and new revisions over the last three years.


  • What does the system have to do?
    • list the basic objective and requirements of the system
  • What is its basic interface with other systems?
    • list the systems needed interface with other systems
  • This info is the most important part of the systems documentation, I dont really care how you document it (word file, excel file, wiki, etc) just document it

Pre Schematic Capture (ie Component selection)

  • look for parts that can simplify the system by integrating many of your requirements in a single chip, very little of what we do has not been done before and industry has a nice habit of solving most of your problems in one chip.
    • Find parts with high temperature ranges and ideally low power consumption
    • Error detection is a very nice added benefit
    • You MUST read each chips Errata!
  • Find typical application circuits in the data sheets of the components selected
  • develop a schematic and footprint library in Altium for all of the chips you will be using
    • link the supplier in the schematic library to make your life easier at the end

After Schematic Capture

  • Take a step back, is the system overly complicated?
    • try and remove overly complicated circuits as the are commonly just sources for failures
  • Is there an adequate amount of test points to verify the circuit is working?
    • nothing is more frustrating than debugging a comms interface than having absolutely no access to monitor what the physical connections are doing
  • Check All comms interfaces
    • list all addresses on an I2C bus, are there any collisions?
      • this is also amazingly helpful for firmware programming so keep the list somewhere in your documentation with the interface definition
    • Do all SPI devices have a unique chip select?
    • Are UART interfaces operating at the same voltage?
    • Do you have enough PWM/ADC/DAC/etc connections?
      • is there anything in a chips documentation that prevents two different connections from working at the same time?
  • Have you actually read the chips data sheets and errata and understood how to connect them? or did you just copy the first application circuit?
  • Have you added ESD protection on any inputs leading close to the structure? have sensitive signal lines been filtered for EMI?

Before claiming layout is complete

  • Check that soldermask is reasonable
    • ie not over pads oriented in a consistent way
    • Soldermask has been added to indicate test points
    • System name and revision number have been added
  • Run the bloody design rule check
    • this should catch all unrouted nets, shorts, and bad clearances.
  • Check that higher power components have a good ground connection that can allow temperature to transfer to the structure
    • We have no convection in space and the board is the only way to transfer thermal energy.
  • Is the stack connector in the correct place?
    • X=4200mil, Y=5500mil, Rotation 270, relative to absolute origin
    • Is the correct schematic sheet included for the stack connector
  • Is the board outline defined on mechanical layer 2?
    • it should be the only primitive on that layer

After layout

  • Create Gerber Files
    • Was the origin reset before creating Gerber files?
    • should be 2.4 with leading zeros suppressed
  • Create NC drill file
    • An Excellon format NC drill file will need to be provided as well. 2.4 trailing format.
  • Create a Read.ME file in text format
    • List of every file name with a brief description as to what it is.
    • List all non-Gerber specs for this job, if not included in a fab. print
    • Your contact information (include evening phone if you like)
  • Create your bill of materials
    • if you did the schematic and footprint library step correctly you should only need to update the passives (resistors, capacitors, inductors) and everything else will already be linked to the distributors database.

Layout rules


Advaced Circuits Tolerances

  • Clearance
    • 6 mil minimum between all
  • Trace Width
    • 7 mil minimum Trace Width
  • Finished Hole Size
    • 8 mil minimum hole size
  • Pad size/Annual Ring
    • 5mil for Via’s
    • 7mil for through holes
  • Polygon Connect
    • Bus connection
      • Direct Connection for GND
    • Via’s
      • Direct Connection for GND

Enigma ?

QR Code
QR Code altium_checklist (generated for current page)